1. Field of the Invention
The present invention relates to a simulator for checking the timing errors of the devices in a simulated circuit while simulating the devices of the simulated circuit.
2. Description of the Prior Art
In the design of logical circuits, logical simulators are frequently used as checking means of logical operations and timing of the devices therein. There are also simulators exclusively used for the checking of timing.
FIG. 1 is a flow chart showing timing check operations in a conventional simulator. The operations of the simulator will be described below with reference to the flow chart.
First, in step S1, a process of inputting an input test pattern signal to an input terminal of a simulated circuit is simulatively executed in the simulator. The simulator executes the simulation of the simulated circuit by calculating the output value corresponding to the input value of each device. Then, in step S2, the simulator checks the timing error in the input and output signals of each device of the simulated circuit on the basis of the results of the simulation obtained in the step S1.
When it is decided in step S3 that a timing error has occurred, the simulator moves to step S4. In the step S4, the simulator outputs an error message list, inclusive of the kind of the timing error, the time when the error occurred, the name of the device on which the error occurred, etc., serving as a reference for making clear the cause of the timing error. On the other hand, when it is decided in the step S3 that no timing error has occurred, the simulator advances directly to step S5.
The simulator, in the step S5, checks whether or not all the devices within the simulated circuit have gone through the simulation, and if there is any device which has not gone through the simulation, it returns to the step S1. The steps S1-S5 are repeated until all of the devices have been subjected to the simulation. Thus, the timing check is performed by the simulator.
Conventional simulators have performed the timing error check of all of the devices as objects of timing error check and output the timing error messages as described above.
Generally speaking, a high simulating speed is required of the simulator, and therefore, the period of time required for the timing check must be limited to a minimum so as not to impair the operating speed. Accordingly, there has been a problem with conventional simulators in that they are only able to check the timing error as to limited check items and unable to perform detailed timing error checking.